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TOSHIBA
TLCS-90 Series
TMP90C800/801
CMOS 8-Bit Microcontrollers TMP90C800N/TMP90C801N TMP90C800F/TMP90C801F
1. Outline and Characteristics The TMP90C800 is a high-speed advanced 8-bit microcontroller applicable to a variety of equipment. With its 8-bit CPU, ROM, RAM, timer/event counter and general-purpose serial interface integrated into a single CMOS chip, the TMP90C800 allows the expansion of external memories for programs and data (up to 56K bytes). The function of TMP90C800 is exactly same as the TMP90C400 except the internal ROM/RAM size. The TMP90C801 is the same as the TMP90C800 but without the ROM. The TMP90C800N/801N is in a shrink Dual Inline Package (SDIP64-P-750). The TMP90C800F/801F is in a Quad Flat package (QFP64-P-1420A) The characteristics of the TMP90C800 include: (1) Powerful instructions: 163 basic instructions, including Multiplication, division, 16-bit arithmetic operations, bit manipulation instructions Minimum instruction executing time: 320ns (at 12.5MHz oscillation frequency)
(3)
(2)
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Internal ROM: 8K bytes (The TMP90C801 does not have a built-in ROM) (4) Internal RAM: 256 bytes (5) Memory expansion External memory: 56K bytes (6) General-purpose serial interface (1 channel) Asynchronous mode, I/O interface mode (7) 8-bit timers (4 channel): (2 external clock input) (8) Port with zero-cross detection circuit (4 input) (9) Input/Output ports (56 pins) - Ports with programmable pull-up resistor (22 pins) - Allows I/O selection on bit basis - Multiplexer ports of address data bus (10) Interrupt function: 7 internal interrupts and 3 external interrupts (11) Micro Direct Memory Access (DMA) function (8 channels) (12) Standby function (4 HALT modes)
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The information contained here is subject to change without notice. The information contained herein is presented only as guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. These TOSHIBA products are intended for usage in general electronic equipments (office equipment, communication equipment, measuring equipment, domestic electrification, etc.) Please make sure that you consult with us before you use these TOSHIBA products in equipments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traffic signal, combustion control, all types of safety devices, etc.). TOSHIBA cannot accept liability to any damage which may occur in case these TOSHIBA products were used in the mentioned equipments without prior consultation with TOSHIBA.
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Figure 1. TMP90C800 Block Diagram
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2. Pin Assignment and Functions
This section describes the assignment of input/output pins, their names and functions.
2.1 Pin Assignment Figure 2.1 shows pin assignment of the TMP90C800N/801N.
Figure 2.1 (1). Pin Assignment (Shrink Dual Inline Package)
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Figure 2.1 (2) shows Pin Assignment of the TMP90C800F/ 801F.
Figure 2.1 (2). Pin Assignment (Flat Package)
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2.2 Pin Names and Functions The names of input/output pins and their functions are summarized in Table 2.2.
Table 2.2 Pin Names and Functions (1/2)
Pin Name
P00 ~ P07 /AD0 ~ AD7
No. of pins
8
I/O 3 states
I/O 3 states I/O
Function
Port 0: 8-bit I/O port that allows selection of input/output on byte basis Address/Data bus: Functions as 8-bit bidirectional address/data bus for external memory (For 401, fixed to address/data bus) Port 1: 8-bit I/O port that allows selection on byte basis Address bus: Functions as address bus (upper 8 bits) by EXT1 set for external memory (For 401, fixed to address bus Port 20 ~ 23: 4-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Port 24: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Non-maskable interrupt request pin: Falling edge interrupt register pin
P10 ~ P17 /A8 ~ A15 P20 ~ P23
8
Output I.O I/O
4
P24 /NMI
1 Input
P25 /WAIT P26 /RD P27 /WR
1
I/O Input
Port 25: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Wait: Input pin for connecting slow speed memory of peripheral LSI Port 26: 1-bit output port Read: Generates strobe signal for reading external memory (For 401, fixed to RD) Port 27: 1-bit output port Read: Generates strobe signal for writing into external memory (For 401, fixed to WR) Port 30: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Interrupt request pin 0: Interrupt request pin (Level/rising edge is programmable)
1
Output Output Output Output I/O
1
P30 /INTO
1 Input
P31 /INT1
Port 31: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis 1 Input Interrupt request pin 1: Rising edge interrupt request pin
P32 /TI0
1
I/O Input
Port 32: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Timer input 0: Counter input pin for Timer 0 Port 33: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Timer input 2: Counter input pin for Timer 2
P33 /TI2
1
Output
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Table 2.2 Pin Names and Functions (2/2)
P35 /RxD 1 I/O I/O 1 I/O Output 1 8 8 8 1 1 1 1 2 1 1 I/O Output I/O I/O I/O Output Input Output Input Input/Output - - Port 35: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Receive serial data Port 36: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Serial clock output Port 37: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Transmitter serial data Port 4: 8-bit I/O port that allows I/O selection on bit basis Port 5: 1-bit I/O port with a pull-up resistor that can be programmed, and allows selection of input/output on bit basis Port 6: 8-bit I/O port that allows I/O selection on bit basis Address latch enable signal: The negative edge ALE supplies an address latch timing on AD0 ~ A07 for external memory External access: Connects with VCC pin in the TMP90C400 using internal ROM, and with GND pin in the TMP90C401 with no internal ROM Clock output: Generates clock pulse at 1/4 frequency of clock oscillation. It is pulled up internally during resetting. Reset: Initializes the TMP90C400/401 (Built-in pull-up resistor) Pin for quartz crystal or ceramic resonator (1 ~ 12.5MHz) Power supply (+5V) Ground (0V)
P36 /SCLK
P37 TxD P40 ~ P47 P50 ~ P57 P60 ~ P67 ALE EA CLK RESET X1/X2 VCC VSS
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3. Operation
This chapter describes the functions and the basic operations of the TMP90C400/401 in every block. The function of TMP90C800 is exactly same as that of TMP90C400 except the internal ROM/RAM size. Refer to the TMP90C400 except the function which are not described this section. 3.1 CPU The TMP90C800 includes a high performance 8-bit CPU. For the function of the CPU, see the book TLCS Series CPU Core Architecture concerning CPU operation. 3.2 Memory Map The TMP90C800 supports a program memory of up to 56K bytes. The program and data memory may be assigned to the address space from 0000H to FFFFH. (1) Internal ROM The TMP90C800 internally contains an 8K-byte ROM. The address space from 0000H to 1FFFH is provided to the ROM. The CPU starts executing a program from 0000H by resetting. The addresses 0010H to 005FH in this internal ROM area are used for the entry area for the interrupt processing. The TMP90C801 does not have a built-in ROM; therefore, the address space 0000H to 1FFFH is used as external memory space.
(2)
Internal RAM The TMP90C800 also contains a 256-byte RAM, which is allocated to the address space from FF80H to FF7FH. The CPU allows the access to a certain RAM area (FF00H to FF7FH, 256 bytes) by a short operation code (opcode) in a "direct addressing mode". The addresses from FF20H to FF5FH in this RAM area can be used as parameter area for micro DMA processing (and for any other purposes when the micro DMA function is not used).
(3)
Internal I/O The TMP90C800 provides a 32-byte address space as an internal I/O area, whose addresses range from FF80H to FF9FH. This I/O area can be accessed by the CPU using a short opcode in the "direct addressing mode". Figure 3.1 is a memory map indicating the areas accessible by the CPU in the respective addressing mode.
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Figure 3.2 (a). Memory Map of TMP90C800
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Figure 3.2 (b). Memory Map of TMP90C801
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4. Electrical Characteristics (Preliminary)
TMP90C800N/TMP90C800F/ TMP90C801N/TMP90C801F 4.1 Absolute Maximum Ratings
Symbol
VCC VIN PD TSOLDER TSTG TOPR Supply voltage Input voltage Power dissipation (Ta = 85C) Soldering temperature (10s) Storage temperature Operating temperature
Parameter
Rating
-0.5 ~ + 7 -0.5 ~ VCC + 0.5 F 500 N 600 260 -65 ~ 150 -40 ~ 85
Unit
V V mW C C C
4.2 DC Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70C (1 ~ 12.5MHz) Symbol
VIL VIL1 VIL2 VIL3 VIL4 VIH VIH1 VIH2 VIH3 VIH4 VOL VOH VOH1 VOH2 IDAR ILI ILO Input Low Voltage (P0) P1, P2, P3, P4, P5, P6 RESET, NMI EA X1 Input High Voltage (P0) P1, P2, P3, P4, P5, P6 RESET, NMI EA X1 Output Low Voltage Output High Voltage Darlington Drive Current (8 I/O pins) (Note) Input Leakage Current Output Leakage Current Operating Current (RUN) Idle 1 Idle 2 ICC STOP (TA = -40 ~ 85C) STOP (TA = 0 ~ 50C) Power Down Voltage (@STOP) RESET Pull Up Register Pin Capacitance Schmitt width RESET, NMI
Parameter
Min
-0.3 -0.3 -0.3 -0.3 -0.3 2.2 0.7VCC 0.75VCC VCC - 0.3 0.8VCC - 2.4 0.75VCC 0.9VCC -0.1 0.02 (Typ) 0.05 (Typ) 20 (Typ) 1.5 (Typ) 6 (Typ) 0.05 (Typ) 2 RAM BACK UP 50 - 0.4
Max
0.8 0.3VCC 0.25VCC 0.3 0.2VCC VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 0.45 -
Unit
V V V V V V V V V V V V V V mA A A mA mA mA A A V K pF V
Test Conditions
- - - - - - - - - - IOL = 1.6mA IOH = -400A IOH = -100A IOH = -20A VEXT = 1.5V REXT = 1.1k 0.0 Vin VCC 0.2 Vin VCC - 0.2 tosc = 10MHz (25%Up @12.5MHz) 0.2 Vin VCC - 0.2 VIL2 = 0.2VCC, VIH2 = 0.8VCC - testfreq = 1MHz -
-3.5 5 10 40 5 15 50 10 6 150 10 1.0 (Typ)
VSTOP RRST CIO VTH
Note: IDAR is guaranteed for a total of up to 8 optional ports.
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4.3 AC Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol
tOSC tCYC tWH tWL tAL tLA tLL tLC tCL tACL tACH tCA tADL tADH tRD tRR tHR tRAE tWW tDW tWD tACKH tACKL tCKHA tCCK tCKHC tDCK tCWA tAWAL tWAH tAWAH tCPW tPRC tCPR Oscillation cycle ( = x) CLK Period CLK High width CLK Low width A0 ~ 7 effective addressALE fall ALE fall A0 ~ 7 hold ALE Pulse width ALE fall RD/WR fall RD/WR ALE rise A0 ~ 7 effective address RD/WR fall Upper effective address RD/WR fall RD/WR fall Upper address hold A0 ~ 7 effective address Effective data input Upper effective address Effective data input RD fall Effective data input RD Pulse width RD rise Data hold RD rise Address enable WR pulse width Effective dataWR rise WR riseEffective data hold Upper addressCLK fall Lower address CLK fall CLK fallUpper address hold RD/WRCLK fall CLK fallRD/WR rise Valid data CLK fall RD/WR fallValid WAIT Lower address Valid WAIT CLK fall Valid WAIT hold Upper address Valid WAIT CLK fall Port Data Output Port Data Input CLK fall CLK fall Port Data hold
10MHz Clock Min
100 400 160 160 35 35 60 20 30 75 100 30 - - - 160 0 85 160 150 40 200 150 70 75 40 50 - - 0 - - 200 100
12.5MHz Clock Unit Min
80 320 120 120 25 25 40 10 20 55 70 20 - - - 120 0 65 120 110 30 150 110 40 55 20 30 - - 0 - - 200 100
Parameter Min
80 4x 2x - 40 2x - 40 0.5x - 15 0.5x - 15 x - 40 0.5x - 30 0.5x - 20 x - 25 1.5x - 50 0.5x - 20 - - - 2.0x - 40 0 x - 15 2.0x - 40 2.0x - 50 0.5x - 10 2.5x - 50 2.0x - 50 1.5x - 80 x - 25 x - 60 x - 50 - - 0 - - 200 100
Max
1000 4x - - - - - - - - - - 3.0x - 35 3.5x - 55 2.0x - 50 - - - - - - - - - - - - x - 40 2.0x - 70 - 2.5x - 70 x + 200 - -
Max
- - - - - - - - - - - - 265 295 150 - - - - - - - - - - - - 60 130 - 180 300 - -
Max
- - - - - - - - - - - - 205 225 110 - - - - - - - - - - - - 40 90 - 130 280 - - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
AC Measuring Conditions * Output level: High 2.2V/Low 0.8V, CL = 50pF (However, CL = 100pF for AD0 ~ 7, A8 ~ 15, ALE, RD, WR) * Input level: High 2.4V/Low 0.45V (AD0 ~ AD7) High 0.8VCC/Low 0.2VCC (excluding AD0 ~ AD7)
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4.4 Zero-Cross Characteristics
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70C (1 ~ 12.5MHz) Symbol
VZX AZX FZX
Parameter
Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency
Condition
AC coupling C = 0.1F 50/60Hz sine wave -
Min
1 - 0.04
Max
1.8 135 1
Unit
VAC p-p mV kHz
4.5 Serial Channel Timing-I/O Interface Mode
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) CL = 50pF TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol
tSCY tOSS tOHS tHSR tSRD
10MHz Clock Max
- - - -
12.5MHz Clock Unit Min
640 330 40 0 -
Parameter Min
Serial Port Clock Cycle Time Output Data Setup SCLK Rising Edge Output Data Hold After SCLK Rising Edge Input Data Hold After SCLK Rising Edge SCLK Rising Edge to Input DATA Valid 8x 6x - 150 2x - 120 0 -
Min
800 450 80 0 -
Max
- - - - 450
Max
- - - - 330 ns ns ns ns ns
6x - 150
4.6 8-bit Event Counter
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol
tVCK tVCKL tVCKH TI2 clock cycle TI2 Low clock pulse width TI2 High clock pulse width
10MHz Clock Max
- - -
12.5MHz Clock Unit Min
740 360 360
Parameter Min
8x + 100 4x + 40 4x + 40
Min
900 440 440
Max
- - -
Max
- - - ns ns ns
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4.7 Interrupt Operation
VCC = 5V 10% TA = -40 ~ 85C (1 ~ 10MHz) TA = -20 ~ 70C (1 ~ 12.5MHz) Variable Symbol Parameter Min
NMI, INT0 Low level pulse width tINTAL NMI, INT0 High level pulse width 4x - 400 - 320 - ns
10MHz Clock Max Min Max
12.5MHz Clock Unit Min Max
tINTAH
4x
-
400
-
320
-
ns
INT1, INT2 Low level pulse width tINTBL INT1, INT2 High level pulse width tINTBH 8x + 100 - 900 - 740 - ns 8x + 100 - 900 - 740 - ns
4.8 I/O Interface Mode Timing
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4.9 Timing Chart
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